1) Field of the Invention
This invention relates to a clock distribution circuit for a semiconductor integrated circuit such as an LSI wherein a large number of cells are arranged on a chip of a rectangular shape including a square shape for distributing a clock signal to those cells each of which has a clock terminal, and more particularly to a clock distribution circuit suitable for use with a chip of the building block type which includes a RAM and/or a large number of huge macro blocks.
2) Description of the Related Art
Generally, a semiconductor integrated circuit such as, for example, an LSI entirely operates in synchronism with a single clock signal or a plurality of clock signals having different phases from each other. In such an instance, a clock signal or signals supplied from the outside are distributed to flip-flops (cells each having a clock terminal) of various circuits in the LSI to allow such operations as decoding, reading/writing of memories and calculation. However, where the wiring line lengths from the distribution source or sources of the clock signal or signals to the distribution destinations are different from each other, some displacements (clock skews) appear among arriving timings of the clock signal or signals. If a clock skew appears, then a flip-flop may fetch a wrong signal or a logic gate may generate an undesirable hair-shaped pulse at an output thereof, resulting in malfunction of a circuit. Accordingly, the magnitude of a clock skew makes a factor which determines the performance (operation speed) of the LSI.
Therefore, such an H-shaped clock distribution system as shown in FIG. 4 is usually employed in a semiconductor integrated circuit such as an LSI. Referring to FIG. 4, the H-shaped clock distribution system shown includes a plurality of stages (three stages in FIG. 4) of buffers 102 to 104 provided on a rectangular (square) chip 100. The buffers 102 to 104 are connected to each other in a tree-like configuration by H-shaped clock wiring lines 106 and 107.
More particularly, an input driver 101 for receiving a clock signal from the outside is provided at the center of one side (left side in FIG. 4) of a peripheral region of the chip 100. An output of the input driver 101 is inputted to the first buffer 102 disposed at the center of the chip 100 by a clock wiring line 105.
An output of the first buffer 102 is inputted to the four second buffers 103 by the H-shaped clock wiring line 106 which is centered at the first buffer 102. The second buffers 103 are individually disposed at four terminal ends of the H-shaped clock wiring line 106. Consequently, the wiring line lengths from the first buffer 102 to the four second buffers 103 are equal to each other.
Each of outputs of the second buffers 103 is inputted to four ones of the third buffers 104 by one of the H-shaped clock wiring lines 107 which is centered at the second buffer 103. The third buffers 104 are disposed at four terminal ends of the H-shaped clock wiring line 107, and consequently, the wiring line lengths from the second buffer 103 to the four third buffers 104 are equal to each other.
Since the buffers 102 to 104 are connected in such a manner as described above by the clock wiring lines 106 and 107, a clock signal is distributed to the 16 third buffers 104 disposed substantially in a uniform density in a cell arrangement region of the chip 100 and is then supplied from the third buffers 104 to the clock terminals of flip-flops or like elements. In this instance, the wiring line lengths from the first buffer 102 to the third buffers 104 are all equal to each other, and consequently, clock skews at the buffers 104 in the last stage can be made uniform. It is to be noted that the third buffers 104 may be connected to further buffers by H-shaped clock wiring lines to further distribute the clock signal to the further buffers.
Another clock distribution system is disclosed, for example, in Japanese Patent Laid-Open Application No. Heisei 4-373160, and is shown in FIG. 5. Referring to FIG. 5, the clock distribution system shown includes a plurality of stages (three stages in FIG. 5) of buffers 202 to 204 provided on a square chip 200. The buffers 202 to 204 are connected to each other in a tree-like configuration by clock wiring lines 206 and 207, and outputs of the four third buffers 204 are all connected commonly to a wiring line 208.
More particularly, an input driver 201 for receiving a clock signal from the outside is provided on one side (left side in FIG. 5) of a peripheral region of the chip 200. An output of the input driver 201 is inputted to the first buffer 202 disposed at one corner portion (left lower corner portion in FIG. 5) of the peripheral region of the chip 200 by a clock wiring line 205.
An output of the first buffer 202 is inputted to the two second buffers 203 disposed at a left upper corner portion and a right lower corner portion of the peripheral region of the chip 200 over the clock wiring lines 206. Here, the wiring line lengths from the first buffer 202 to the second buffers 203 are equal to each other.
An output of the second buffer 203 located at the left upper corner portion is inputted to the two third buffers 204 arranged at the center of the upper side and the center of the left side of the peripheral region of the chip 200 over the clock wiring lines 207. Meanwhile, an output of the second buffer 203 located at the right lower corner portion is inputted to the two third buffers 204 disposed at the center of the lower side and the center of the right side of the peripheral region of the chip 200 over the clock wiring lines 207. Also here, the wiring line lengths from the second buffers 203 to the third buffers 204 are all equal to each other.
Further, outputs of the four third buffers 204 are all connected commonly by the wiring line 208 which is formed in such a manner as to surround a cell arrangement area 209 on the chip 200. A clock signal to be supplied to clock terminals in the cell arrangement area 209 is extracted from the wiring line 208.
In the clock distribution system described above with reference to FIG. 5, since the wiring line lengths from the first buffer 202 to the third buffers 204 are equal to each other and the outputs of the third buffers 204 in the last stage are connected commonly by the wiring line 208 to extract a single output, clock skews at the third buffers 204 in the last stage can be made uniform and also the driving capacity of the entire circuitry can be raised.
By the way, in recent years, an increase in clock frequency has proceeded, and, for example, for a chip which operates with a clock signal of a frequency of several hundreds MHz, it is demanded to suppress the clock skew to the level of several tens picoseconds. In order to satisfy the demand for such a low skew using such an H-shaped clock distribution system as shown in FIG. 4, the clock wiring lines must be wired in substantially a perfect H-shaped configurations and the buffers in the last stage (third buffers 104 in FIG. 4) must be arranged in a uniform density in the cell arrangement area of the chip.
Further, an increase in density and scale of a semiconductor integrated circuit such as an LSI has proceeded to such a degree that a chip sometimes includes up to one million gates. In such an instance, it is difficult for a designer to handle all of such gates uniformly, elements on the chip are blocked to effect hierarchical designing. In particular, different macro blocks whose are different in size and/or shape from each other are first designed individually, and then the macro blocks and macro elements which originally have large sizes such as a RAM are mapped on the chip to design a semiconductor integrated circuit. It is to be noted that such a design type as just described is called building block type.
However, in a chip of the building block type, since it includes a large number of blocks (for example, a RAM, huge macro blocks and so forth) having different sizes, such a situation that, for example, a macro block is present in a region in which an H-shaped clock distributing buffer should be arranged is likely to occur, and it is difficult to lay clock wiring lines of a completely H-shaped configuration. Then, where the H-shaped clock distribution method is applied, the balance of the clock distribution system (uniformity in wiring line length) is lost at all, and a large clock skew is produced. Where blocks of various sizes are arranged on a chip, it makes a significant restriction to designing of the chip to arrange buffers in the last stage in a uniform density and simultaneously make the lengths of all clock wiring lines to individual clock terminals uniform.
Meanwhile, with the clock distribution system shown in FIG. 5, while it is possible to make clock skews at the output terminals of the third buffers 204 uniform, no countermeasure is taken against skews which are produced by distributing a clock signal from the output terminals of the third buffers 204 to clock terminals of flip-flops or like circuit elements in the cell arrangement area 209, and skews appear at the clock terminals of such flip-flops or macro blocks arranged in the cell arrangement area 209. In order to prevent production of clock skews with certainty, buffers must be arranged in a density as uniform as possible also in the inside of the chip (in the actual cell arrangement area 209) and the lengths of clock wiring lines to the clock terminals of the buffers must be made uniform. However, Japanese Patent Laid-Open Application No. Heisei 4-373160 is quite silent of such design.